1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices. More particularly, the invention relates to phase change memory devices and methods for applying a program current.
2. Discussion of Related Art
Phase change memory devices are one class of nonvolatile memory devices. Instead of storing electrical charge to indicate a date value, as is done in other nonvolatile memory devices, the state of a phase change material, such as Ge—Sb—Te (GST), is used to indicate a data value.
Figure (FIG.) 1 is a circuit diagram illustrating a memory cell 10 in a conventional phase change memory device. Memory cell 10 includes a memory element 11 and a select element 12 connected in series between a bitline BL and ground.
Memory element 11 includes a phase change material which functions as a variable resistor in accordance with applied temperature. That is, the phase change material is responsive to resistive heating induced by current applied via bitline BL. Under the influence of this programming technique, the phase change material may be placed in one of two stable resistive states, namely, a crystalline state or an amorphous state.
In the illustrated example, select element 12 is implemented as an NMOS transistor NT having a gate connected to a wordline WL. When a predetermined voltage is applied to the wordline WL, the NMOS transistor NT is turned ON. When the NMOS transistor NT is turned ON, memory element 11 receives a current through the bitline BL. In FIG. 1, memory element 11 is coupled between the bitline BL and the select element 12. However, the select element 12 may alternately be coupled between the bitline BL and the memory element 11.
FIG. 2 is a circuit diagram illustrating another memory cell 20 of a conventional phase change memory device. Memory cell 20 includes a memory element 21 and a select element 22 connected in series between a bitline BL and a wordline WL. Memory element 21 may be identical to memory element 11 of FIG. 1.
In the example illustrated in FIG. 2, select element 22 is implemented as a diode D. Memory element 21 is connected to the anode of the diode D, and the wordline WL is connected to its cathode. When a voltage difference between the anode and cathode of the diode D rises above a defined threshold voltage, the diode D is turned ON. When the diode D is turned ON, memory element 21 receives a current via the bitline BL.
FIG. 3 is a graph illustrating the heating characteristics of the phase change material (e.g., GST) of FIGS. 1 and 2. In FIG. 3, reference numeral 1 denotes a condition wherein the phase change material enters an amorphous state, and reference numeral 2 denotes a condition wherein the phase change material enters a crystalline state.
Referring to FIG. 3, when electrical current is applied to the phase change material such that its temperature rises above a defined melting point temperature TM during a first time period T1, the phase change material is said to be “quenched,” and the phase change material enters its amorphous state. The amorphous state is generally referred to as a reset state and is conventionally equated with a data value of ‘1’.
In contrast, when the phase change material is heated to and held at a predetermined temperature lower than the melting point temperature TM but higher than a crystallization temperature Tc during a second time period T2 longer than the first time period T1, and thereafter slowly cooled, the phase change material enters its crystalline state. The crystalline state is generally referred to as a set state and is conventionally equated with a data value of ‘0’. The resistance of the memory cell is changed in accordance with the amorphous volume of the phase change material. Thus, the resistance of the phase change material forming the memory cell is higher in its amorphous state than in its crystalline state.
The phase change memory device is associated with a write driver circuit supplying a program current to the phase change material during program operations. The write driver circuit supplies the program current, ranging nominally between a set current and a reset current, to the memory cell. The program current in conventionally developed in relation to an externally applied power voltage, (e.g., 2.5 V or higher). The set current forces the phase change material of the memory cell into a set state, and the reset current forces the phase change material of the memory cell into a reset state.
FIG. 4 is a circuit diagram illustrating one possible write driver circuit 30 conventionally applied to phase change memory devices. This write driver circuit 30 is disclosed in some additional detail in Korean Patent Application No. 2003-35607. However, as summarized here, write driver 30 includes a pulse control circuit 31, a current control circuit 32, and a current driving circuit 33. Pulse control circuit 31 includes first and second transmission gates TG1 and TG2, and first through third inverters INV1˜INV3. Current control circuit 32 includes first through seventh transistors TR1˜TR7, first through fifth transistors TR1˜TR5 being NMOS transistors, sixth and seventh transistors TR6 and TR7 being PMOS transistors. Current driving circuit 33 includes a pull-up transistor PUTR and a pull-down transistor PDTR.
First, a program operation for input data DATA having a value of ‘0’ will be described. When the input data DATA is ‘0’, the second transmission gate TG2 of pulse control circuit 31 is turned ON, and the third and fourth transistors TR3 and TR4 of current control circuit 32 are turned OFF. In response to a set pulse P_SET, the fifth transistor TR5 is turned ON, and the seventh transistor TR7 and the pull-down transistor PDTR are turned OFF. Due to the current mirror effect, a current flowing through transistors TR1, TR2, TR5 and TR6 forming a first current path flows through a pull-up transistor PUTR. The current flowing through the pull-up transistor PUTR is a set current I_SET, and is provided to a memory cell MC through a data line DL.
Next, a program operation for input data DATA having a value of ‘1’ will be described. When the input data DATA is ‘1’, the first transmission gate TG1 of pulse control circuit 31 and the third and fourth transistors TR3 and TR4 of current control circuit 32 are turned ON. In response to a reset pulse P_RST, the fifth transistor TR5 is turned ON, and the seventh transistor TR7 and the pull-down transistor PDTR are turned OFF. Due to the current mirror effect, a current flowing through transistors TR1, TR2, TR5 and TR6 forming a first current path and a current flowing through the transistors TR3, TR4, TR5 and TR6 forming a second current path flows through a pull-up transistor PUTR. The current flowing through the pull-up transistor PUTR is a reset current I_RST, and is provided to the memory cell MC through the data line DL.
Therefore, the reset current I_RST is greater than the set current I_SET. Meanwhile, the reset pulse P_RST has a smaller pulse width than the set pulse P_SET. That is, the reset current I_RST has a greater current value and smaller pulse width than the set current I_SET. A selected memory cell is programmed such that it enters the reset state or the set state according to the reset current I_RST or the set current I_SET, correspondingly.
To program data a ‘1’ or ‘0’ in the foregoing phase change memory device, it is necessary to control the magnitude and duration of the program current in accordance with the value of the data being stored. The conventional write driver circuit 30 illustrated in FIG. 3 provides both the set current and the reset current using a single current driving circuit 33. That is, the conventional write driver circuit has a structure that commonly controls the set current and the reset current using a single current mirror circuit. In the set program operation, the current flowing through the first current path is provided to the memory cell MC. In the reset program operation, the current flowing through the first and second current paths is provided to the memory cell MC.
In the reset program operation, the conventional write driver generates a current of about 0.15 to 0.2 milliampere flowing through the second current path, and a current of about 1.0 milliampere flowing through current driving circuit 33 as well as the current flowing through the first current path. That is, in the reset program operation, the conventional write driver requires a higher current than that required for the set program operation by about 1.2 milliampere. In the above-described example, although the conventional write driver requires a current of about 1 milliampere in the reset program operation, there is a problem in that a current of about 0.12 milliampere is unnecessarily consumed through the second current path.